1. Field of the Invention
This invention relates to systems and processes for writing and reading analog or multilevel digital signals in a non-volatile semiconductor memory cell.
2. Description of Related Art
Three common types of non-volatile memory, such as EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), and flash memory use charge on a memory cell's floating gate to control the threshold voltage of the memory cell and indicate the state of the cell. Typically, binary memory cells have two states, one indicated by a high threshold voltage and one indicated by a low threshold voltage. Gathering electrons on a memory cell's floating gate increases the cell's threshold voltage and is referred to as writing or programming the memory cell. Erasing a memory cell removes electrons from the floating gate and reduces the threshold voltage.
EPROM is more than 20 years old and is popular for program storage because EPROM is inexpensive, is non-volatile, and allows code updates using an EPROM programmer system. FIG. 1a shows a conventional stacked-gate EPROM cell 150 which stores charge on a polysilicon floating gate 156 which is buried between an oxide layer 154 and an interpoly oxide layer 157. A control gate 158 capacitively couples to floating gate 156, and changing the voltage on control gate 158 changes the voltage on floating gate 156 which in turn controls current in a channel 160 between a source 162 and a drain 164 in a substrate 152.
Channel Hot Electron (CHE) injection injects energetic (or "hot") electrons from channel 160 into floating gate 156 during writing of EPROM cell 150. CHE injection requires a high voltage at drain 164 to produce hot electrons in channel 160 and a high voltage at control gate 158 to attract electrons into floating gate 156. Typically, an EPROM cell such as memory cell 150 starts with a threshold voltage at an erased or "virgin" level of about 1.5 volts and writing raises the cell's threshold voltage to over 5 volts. EPROM cell 150 is erased by exposure to ultraviolet light for an extended time (typically thirty minutes or longer) which removes electrons from floating gate 156 and returns the threshold voltage of EPROM cell 150 to the virgin level.
EEPROM is electrically erased. FIG. 1b shows a typical EEPROM cell 170 which consists of a floating gate transistor 172 and a separately defined tunneling diode area 174. EEPROM cell 170 also includes a select transistor 175. Writing and erasing of EEPROM rely on Fowler-Nordheim tunneling (FNT) mechanism to add or remove electrons from a floating gate 176. The terminology "flash" comes from the ability to simultaneously electrically erase an entire memory array or a large portion of the memory array in a flash. Flash memories include flash EPROM and flash EEPROM and typically are erased by FNT. Flash EPROM, like EPROM, uses CHE injection for writing. In contrast, flash EEPROM, like conventional EEPROM, relies on FNT for writing.
FIG. 1c shows a conventional N-channel stacked gate flash EPROM cell 100. Flash EPROM cell 100 includes a polysilicon control gate or word line 102 overlying a polysilicon floating gate 101. A high-integrity gate oxide 106, typically less than 100 .ANG. thick, isolates floating gate 101 from an N+ source 103, an N+ drain 104, and a channel 105 formed in a P-type substrate 108. A thin insulator 107 separates control gate 102 and floating gate 101 to provide a high capacitive coupling ratio between control gate 102 and floating gate 101. During a conventional write of flash EPROM cell 100, control gate 102 is raised to about 12 volts, drain 104 is raised to about 5 volts or higher, and source 103 is grounded. At these voltages, hot electrons from current in a portion of channel 105 near drain 104 pass through gate oxide 106 into floating gate 101.
A typical source-side erase of memory cell 100 raises source 103 to a voltage of about 12 volts, grounds control gate 102, and permits drain 104 to float. Electrons from floating gate 101 tunnel through gate oxide 106 into source 103. When a large block of flash EPROM cells are simultaneously source-side erased, a combined band-to-band tunneling current can add up to more than 10 mA, which is beyond the capability of a typical on-chip high-voltage charge-pump circuit that provides 12 volts at source 103. To reduce the band-to-band tunneling current, to increase the gate-aided junction breakdown voltage at the source junction, and to provide a direct tunneling area between the source 103 and the floating gate 101, source 103 is typically deeper in substrate 108 than is drain 104. A deeper source 103 reduces the electric field at the curvature of the junction between source 103 and channel 105, which allows a higher voltage at source 103 during an erase. For certain applications such as audio recording, the band-to-band tunneling current can be further reduced by limiting the number of memory cells within each block to be simultaneously erased.
An alternative erase operation referred to as negative-gate erase, typically requires a negative 12 volts on control gate 102 while source 103 is grounded or at a 5-volt potential. A negative-gate erase allows a power supply, instead of an on-chip high-voltage charge-pump, to provide the band-to-band tunneling current during the erase.
FIG. 1d shows a split gate flash EPROM cell 110 where a control gate 111 overlaps a floating gate 112 and effectively forms the gate of a pass transistor in series with a stacked gate transistor. Split gate cell 110 is typically not self-aligned and is larger than a stacked gate cell such as shown in FIG. 1c. However, the pass transistor makes cell 110 less susceptible to over-erasure. FIG. 1e shows a top view of split gate cell 110 which has a separate erase gate 113 (not shown in FIG. 1d). Erasing memory cell 110 typically relies on floating gate to erase gate tunneling or field emission due to asperities.
FIG. 1f shows a sectional view of what is commonly referred to as a high injection efficiency flash EPROM cell 120. For source-side injection, a polysilicon select gate 121 modulates an enhancement transistor having a channel 124 near source 103 and in series with a stacked gate transistor having a channel 126 modulated by floating gate 123 and control gate 122. Biasing select gate 121 near the enhancement transistor's threshold voltage and control gate 122 at about 12 volts, creates a large surface potential in a weak gate-controlled channel region 125 located between the two transistors. The large surface potential provides a high injection efficiency of hot electrons near source 103. A key advantage of this scheme is a substantial reduction in write current which allows the use of an on-chip high-voltage charge-pump for writing. Erasure relies on either drain-side injection using FNT or a polysilicon-to-polysilicon erase similar to the split gate cell as described in connection with FIG. 1d.
FIG. 1g shows a perspective view of a flash EPROM cell 130 having a single polysilicon layer which forms a floating gate 131. Diffusion or buried diffusion forms a source 133, a drain 134, and a channel 135 in a substrate 108 and a control gate 132 in substrate 108 underlying floating gate 131. Source 133 and drain 134 are separated from control gate 132 by a field oxide region 136. The single polysilicon process for fabricating memory cell 130 is simpler than double or triple polysilicon processes used for memory cells 100, 110, and 120 and is compatible to other ASIC technologies. A disadvantage of memory cell 130 is a large cell size. Memory cell 130 is attractive for applications requiring a small number of memory cells and a single polysilicon layer.
The above-described prior art memory cells are typically used in applications where the threshold voltage of a memory cell indicates one of two binary states of the cell (i.e. a single bit of information). Storing more information in each cell would increase storage capacity of an array. However, writing more than two distinguishable levels in a memory cell requires precise control of writing threshold voltage. Most schemes for writing multi-level threshold voltages in non-volatile memory have used EEPROM and relied on the long write times required for FNT to allow control of writing of threshold voltages. For flash EPROM which use the much faster CHE injection for writing, the prior art has not provided adequate control to permit accurate writing of analog signals. Reading the threshold voltage also requires precision not provided or required by memory arrays containing binary memory cells.